3D Stacked Chips: From Emerging Processes to Heterogeneous by Ibrahim (Abe) M. Elfadel, Gerhard Fettweis

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By Ibrahim (Abe) M. Elfadel, Gerhard Fettweis

This e-book explains for readers how 3D chip stacks promise to extend the extent of on-chip integration, and to layout new heterogeneous semiconductor units that mix chips of alternative integration applied sciences (incl. sensors) in one package deal of the smallest attainable dimension. The authors specialize in heterogeneous 3D integration, addressing the most very important demanding situations during this rising know-how, together with contactless, optics-based, and carbon-nanotube-based 3D integration, in addition to signal-integrity and thermal administration matters in copper-based 3D integration. assurance additionally comprises the 3D heterogeneous integration of energy assets, photonic units, and non-volatile thoughts in accordance with new fabrics systems.

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14) [19]. The investigations on high aspect ratios (AR>10:1) have shown that a deposition of only 5–10 nm TaN barrier layer and a 5–10 nm Ru seed layer is sufficient for subsequent ECD of copper. In this case, 900 nm SiO2 is used as insulator. 4 Electrochemical Deposition Similar to damascene technology, the ECD process in TSV technology uses sulfuric acid–copper sulphate electrolytes with a small amount of chloride anions (usually 30–70 mg/L) and a set of three organic additives: accelerator, suppressor, and leveler.

The high aspect ratio TSV structures were coated with an ALD film stack consisting of a 5–10 nm TaN-based copper diffusion barrier and a 10 nm Ru(C) seed layer for copper plating. The TSVs are either filled or just enhanced with copper in an electrochemical plating process. An additional front and back side lithography is used to generate the metallization layer mask for the subsequent patterning processes. The copper layers on both sides of the interposer are structured in a wet etching process and the redistribution lines on the front and the back side of the wafer are created by pattern plating.

Thermal oxidation of silicon is usually performed at a temperature between 800 and 1200 ı C. Thermal oxide is based on a chemical reaction of oxygen and silicon, and requires the diffusion of the oxidant through the already grown SiO2 to the unreacted Si surface. Here, the silicon is converted by the oxygen to silicon oxide. 27 unit thicknesses of oxide will appear. If a bare silicon surface is oxidized, 44 % of the oxide thickness will lie below the original surface, and 56 % above it. To achieve homogeneous layers by thermal oxidation, the TSV must be free of polymer residues and has to have low surface roughness.

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