By Marvin Onabajo
This ebook describes a number of innovations to deal with variation-related layout demanding situations for analog blocks in mixed-signal systems-on-chip. The tools offered are effects from fresh study works concerning receiver front-end circuits, baseband clear out linearization, and information conversion. those circuit-level ideas are defined, with their relationships to rising system-level calibration methods, to track the performances of analog circuits with electronic advice or keep watch over. assurance additionally contains a technique to make the most of on-chip temperature sensors to degree the sign energy and linearity features of analog/RF circuits, as established by way of try out chip measurements.
- Describes numerous variation-tolerant analog circuit layout examples, together with from RF front-ends, high-performance ADCs and baseband filters;
- Includes integrated checking out options, associated with present commercial trends;
- Balances digitally-assisted functionality tuning with analog functionality tuning and mismatch relief approaches;
- Describes theoretical techniques in addition to experimental effects for try chips designed with variation-aware techniques.
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Additional info for Analog Circuit Design for Process Variation-Resilient Systems-on-a-Chip
The circuit under test (CUT) represents a block in the RF front-end or analog baseband that can be connected to a BIT circuit in test mode by closing the two switches S1 and S2. In  for instance, a low-noise amplifier (LNA) was tested with a BIT block containing a test amplifier and two power detectors to measure input impedance, gain, noise figure, input return loss, and output SNR of the LNA. This approach has the advantage that the fault location/cause can be identified clearly and that the DC or digital outputs of the BIT circuits can be used to recover from certain failure modes.
References 1. C. Chiang, J. Kawa, Design for Manufacturability and Yield for Nano-scale CMOS (Springer, Dordrecht, 2007), pp. 14–15 2. W. Zhao, Y. Cao, F. Liu, K. Agarwal, D. Acharyya, S. Nassif, K. Nowka, Rigorous extraction of process variations for 65 nm CMOS design, in Proceedings of European Solid-State Device Research Conference (ESSDERC), Sept 2007, pp. 89–92 3. W. Roberts, B. Dufort, Making complex mixed-signal telecommunication integrated circuits testable. IEEE Commun. Mag. 90–96 (1999) 4.
Thus, no charge is stored on the floating gates when the substrate contacts are also connected to the top metal layer , allowing gate discharge into the substrate before the last etching operation. After etching, the top metal extensions of the gates without trapped charge are floating, leaving only the connections to the two MIM capacitors. The floating-gate device design expressions for k1 and (1 - k1) above are assuming absence of excess charge on the floating gates, which is a satisfied condition without extra fabrication steps as a consequence of the gate and substrate connections to the top metal.