Analog Integrated Circuit Design Automation: Placement, by Ricardo Martins, Nuno Lourenço, Nuno Horta

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By Ricardo Martins, Nuno Lourenço, Nuno Horta

This booklet introduces readers to various instruments for analog format layout automation. After discussing the location and routing challenge in digital layout automation (EDA), the authors evaluate a number of computerized format iteration instruments, in addition to the latest advances in analog layout-aware circuit sizing. The dialogue contains varied equipment for automated placement (a template-based Placer and an optimization-based Placer), a fully-automatic Router and an empirical-based Parasitic Extractor. The ideas and algorithms of all of the modules are completely defined, permitting readers to breed the methodologies, increase the standard in their designs, or use them as place to begin for a brand new instrument. all of the tools defined are utilized to sensible examples for a 130nm layout technique, in addition to placement and routing benchmark sets.

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Starting from the netlist, if the terminal-to-terminal connectivity of each net is unknown, the routing of single-port multiterminal signal nets is usually addressed as the classical Steiner minimal tree (SMT) problem. Where, a set of Steiner points must be found in order to minimize the SMT total interconnect length that contains all the terminals of the net. This problem is often generalized as the rectilinear Steiner minimal tree (RSMT), when only edges defined by vertical or horizontal segments are considered, however, the problem is still NP-complete [50].

In each iteration, the floorplan is exhaustively explored by enumeration using Plantage [2], and then the best placement, selected based on some performance criteria, is routed and considered for post-layout simulation. 3 Parasitic Extractors Used in Layout-Aware Approaches The parasitic structures extracted from the layout must be precise enough to guide the parasitic-aware circuit sizing in the right direction. In [99] a 1/2-D model is chosen but only applied for the area and fringing capacitance of the metal and poly stripes of the circuit’s critical nets, which makes the estimation quick, but loses accuracy and needs user intervention to identify the critical nets.

Layout retargeting is the process of generating a layout from an existing layout. The main target is to conserve most of the design choices and knowledge of the source design, while: migrating it another given technology; update specifications; or, attempt to optimize the old design [1]. Liu and Zhang [82, 83] developed a tool that automatically conducts performance-constrained parasitic-aware retargeting and optimization of analog layouts. Performance sensitivities with respect to layout parasitics are first determined, and then the algorithm applies a sensitivity model to control parasitic-related layout geometries, by directly constructing a set of performance constraints subject to maximum performance deviation due to parasitics.

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