By Aida Todri-Sanial, Jean Dijon, Antonio Maffucci
This ebook offers a single-source reference at the use of carbon nanotubes (CNTs) as interconnect fabric for horizontal, on-chip and 3D interconnects. The authors display the makes use of of bundles of CNTs, as leading edge engaging in fabric to manufacture interconnect through-silicon vias (TSVs), to be able to enhance the functionality, reliability and integration of 3D built-in circuits (ICs). This ebook may be first to supply a coherent evaluate of exploiting carbon nanotubes for 3D interconnects masking facets from processing, modeling, simulation, characterization and functions. insurance additionally contains a thorough presentation of the appliance of CNTs as horizontal on-chip interconnects which could most likely revolutionize the nanoelectronics undefined. This e-book is a must-read for someone drawn to the cutting-edge on exploiting carbon nanotubes for interconnects for either second and 3D built-in circuits.
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Net 24. Wu F, Levitin G, Hess W (2010) Low-temperature etching of Cu by hydrogen-based plasmas. ACS Appl Mater Interfaces 2:2175–2179 25. Steinhoegl W, Schindler G, Steinlesberger G, Traving M, Engelhardt M (2005) Comprehensive study of the resistivity of copper wires with lateral dimensions of 100 nm and smaller. J Appl Phys 97:023706-1-023706-7 26. Shimada M, Moriyama M, Ito K, Tsukimoto S, Murakami M (2006) Electrical resistivity of polycrystalline Cu interconnects with nanoscale linewidth. J Vac Sci Technol B 24(1):190–194 36 A.
24 A. Ceyhan and A. 96 % between CASE A and CASE B. Therefore, the timing-driven placement and routing tools can compensate for the increasing via resistance if the correct values are provided during the design process. Comparing the results for all cases, there is a monotonic reduction in the number of vias per standard cell and a monotonic increase in the total wirelength. This means that the placement and routing tools work to use a smaller number of vias even though the number of standard cells in the design increases, mainly due to a larger number of buffers, while running longer wires to connect them.
The simulation structure is illustrated in Fig. 6. The barrier material resistivity is assumed to be 500 µ cm. The horizontal run length, Lz , for the top, MU , and bottom, ML , metal levels are assumed to be very small to avoid any impact on the final estimated via resistance value. The misalignment length, Lmis , is calculated as a percentage of the ideal via width and is varied from 0 to 50 % of the width value. The vertical length of via, Lvia , is based on the layer definitions as determined during library construction.