By John Michael Williams
This ebook is dependent as a step by step process examine alongside the traces of a VLSI built-in circuit layout venture. the total Verilog language is gifted, from the fundamentals to every thing beneficial for synthesis of a complete 70,000 transistor, full-duplex serializer-deserializer, together with synthesizable PLLs. the writer contains every thing an engineer wishes for in-depth realizing of the Verilog language: Syntax, synthesis semantics, simulation and try. whole ideas for the 27 labs are supplied within the downloadable documents that accompany the ebook. For readers with entry to acceptable digital layout instruments, all strategies could be built, simulated, and synthesized as defined within the e-book. A partial record of layout subject matters contains layout partitioning, hierarchy decomposition, secure coding types, again annotation, wrapper modules, concurrency, race stipulations, assertion-based verification, clock synchronization, and layout for try. A concluding presentation of specified subject matters contains process Verilog and Verilog-AMS.