Designing TSVs for 3D Integrated Circuits by Nauman Khan

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By Nauman Khan

This booklet explores the demanding situations and offers most sensible thoughts for designing Through-Silicon Vias (TSVs) for 3D built-in circuits. It describes a singular strategy to mitigate TSV-induced noise, the GND Plug, that's more suitable to others tailored from 2-D planar applied sciences, resembling a bottom floor aircraft and standard substrate contacts. The booklet additionally investigates, within the type of a comparative examine, the impression of TSV dimension and granularity, spacing of C4 connectors, off-chip energy supply community, shared and committed TSVs, and coaxial TSVs at the caliber of energy supply in 3-D ICs. The authors offer special most sensible layout practices for designing three-D energy supply networks. considering that TSVs occupy silicon real-estate and effect machine density, this publication presents 4 iterative algorithms to reduce the variety of TSVs in an influence supply community. in contrast to different latest tools, those algorithms might be utilized in early layout phases while purely practical block- point behaviors and a floorplan can be found. ultimately, the authors discover using Carbon Nanotubes for energy grid layout as a futuristic substitute to Copper.

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6 μm2 vs. 4 μm2 ). This huge area penalty, creates large interconnect blockages and reduces the area available for active devices. 2 Backside Ground Plane During assembly and packaging stages, a 2-D die is placed on a grounded metal layer. As mentioned in Sect. 1, the same idea can be extended to 3-D ICs where the substrate has a backside grounded metal, in preferable plate or grid format, creating a strong GND reference for substrate. To model this technique, we add a Cu sheet in the default setup shown in Fig.

8. N. Khan and S. 1 Problem: Power Delivery for 3-D ICs 3-D integration poses grand power delivery challenges for two reasons: increased power density and package asymmetry. Contrast a 3-D IC with a functionally comparable 2-D IC. The average wire length for a 3-D IC drops by a factor of N1/2 where N is the number of dies in the 3-D IC, and the wire resistance and capacitance decreases proportionally [34]. Assuming that the design is interconnect-dominated, power is expected to drop by a factor of N1/2 .

42], where four SPEC workloads (apsi, bzip, equake, and mcf) were run for 100 million instructions using Wattch [21], and 2,048 cycle snippets (8,192 total traces) representing the current patterns were then extracted. Such a power grid evaluation methodology replaces observing millions of instructions from a wide variety of benchmarks, thus significantly saving power grid simulation times. 3 Optimal TSV Size for 3-D PDN We examine in this section how TSV size impacts 3-D power delivery. TSV size is the dimension of one side of the square TSV footprint.

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